In a spectrum analyzer, network analyzer, or the like, for example, there is carried out such a procedure that an input signal is converted to an intermediate frequency signal the frequency of which is one in the range of, for example, 1 MHz to 21.4 MHz or so and then the intermediate frequency signal is converted to a digital signal. In such case, there is required an analog-to-digital conversion apparatus (hereinafter, referred to as A/D conversion apparatus) for converting an input signal to a digital signal, the A/D conversion apparatus having its dynamic range greater than 100 dB as well as higher or faster sampling rate than 42.8 MSa/s (million samples per second). An A/D conversion apparatus that fulfils such requirements is much costly.
An A/D conversion apparatus in which the above-mentioned problem can be solved has been proposed in U.S. Pat. No. 5,844,512 (issued on Dec. 1, 1998). FIG. 1 is a block diagram showing a simplified construction of an A/D conversion apparatus shown in FIG. 4 of U.S. Pat. No. 5,844,512, and there will be now described an outline of the construction and the operation of this A/D conversion apparatus with reference to FIG. 1.
As shown in FIG. 1, an input signal from an input terminal 11 is supplied to an anti-aliasing filter 12 and an envelope detector 14. An input signal that has passed through the anti-aliasing filter 12 is supplied to a variable gain amplifier 13. On the other hand, an input signal inputted to the envelope detector 14 is detected in its envelope by the detector 14, and the detected output is inputted to a gain controller 15 as a proposed gain. The gain controller 15 refers to an output level of the envelope detector 14 and a gain set in the variable gain amplifier 13 to alter and set the gain of the variable gain amplifier 13 so that the output level of the variable gain amplifier 13 comes within a predetermined range. Further, the envelope detector 14 corresponds to the proposed gain detector 48 shown in FIG. 4 of U.S. Pat. No. 5,844,512, and also the gain controller 15 corresponds to the gain setting rule processor 50 shown in FIG. 4 of U.S. Pat. No. 5,844,512.
In such manner as stated above, an input signal is amplified in the variable gain amplifier 13 to a signal the level of which comes within the predetermined range, and the amplified signal is supplied to a sample-and-hold circuit 16. In the sample-and-hold circuit 16, an output signal from the variable gain amplifier 13 is sampled by a sampling clock CKS and the sampled value or data is held therein. The sampled value held in the sample-and-hold circuit 16 is converted by an analog-to-digital converter (hereinafter, referred to as A/D converter) 17 to a digital signal (digital value) which is, in turn, supplied to a correction processing part 18. The correction processing part 18 corrects an inputted digital signal by referring to a look-up table 19 in accordance with an output signal from the gain controller 15. For example, the correction processing part 18 will correct an error in a digital signal that is caused by a shift in the input-output characteristic of the variable gain amplifier 13 from an ideal characteristic thereof, and further, will correct an inputted digital signal to a digital signal showing a level of the input signal before it is amplified by the variable gain amplifier 13 depending upon a gain set to the variable gain amplifier 13. The corrected digital signal is outputted to an output terminal 21 of the correction processing part 18. Further, the correction processing part 18 corresponds to the scaling processor 64 shown in FIG. 4 of the above-stated U.S. Pat. No. 5,844,512.
In the prior art A/D conversion apparatus shown in FIG. 1, the level of an input signal is detected by the envelope detector 14 and the gain of the variable gain amplifier 13 is set depending upon the detected level. Since the envelope detector 14 has a time constant so that a time delay or lag occurs, in the prior art, the anti-aliasing filter 12 is inserted before the variable gain amplifier 13 to remove any aliasing as well as an input signal is delayed by delay means to match a timing when the signal is inputted to the variable gain amplifier 13 to a timing when the detected level of the input signal is inputted to the gain controller 15 so that the level of the input signal can be controlled by the variable gain amplifier 13. However, an input signal undergoes a distortion by the anti-aliasing filter 12 or a delay line unless the group delay thereof is constant and also the frequency characteristic in the amplitude is constant so that it is difficult to convert an input signal to a digital signal with high accuracy.
In addition, since an input signal is detected in its envelope so that the level thereof is detected, as shown in FIG. 2A, for example, when an input signal shown by a solid line 22 is supplied, the gain is set to eight times at the level L1, four times at the level L2, twice at the level L3, and one at the level L4 as shown a broken line 23, and the gain is changed every plural samples. An example of a sample point 24 is illustrated in FIG. 2A by a black point or dot. For this reason, in case of inputting a signal obtained by sweeping or varying the frequency of an input signal; converting the signal to a digital signal; multiplying the digital signal by a digital sine wave signal and a digital cosine wave signal; obtaining the sum of squares of these multiplied values; and finding the frequency characteristic in the amplitude of the input signal, there is obtained, for instance, a waveform the level of which varies stepwise at points 25 where the gain of the variable gain amplifier 13 is changed, that is, a discontinuous waveform as shown in FIG. 2B, and hence a correct display of waveform cannot be obtained.
Moreover, when the gain of the variable gain amplifier 13 is changed, a whisker-like noise (impulse-like noise) or noises are generated in the amplified output signal. If this noise portion should be sampled in the sample-and-hold circuit 16, the noise is sampled so that a false digital signal is outputted.